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gaas, phemt, mmic, 0.25 w power amplifier, dc to 40 ghz data sheet HMC930A rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2015 analog devices, inc. all rights reserved. technical support www.analog.com features high output power for 1 db compression (p1db): 22 dbm high saturated output power (p sat ): 24 dbm high gain: 13 db high output third-order intercept (ip3): 33.5 dbm supply voltage: 10 v at 175 ma 50 matched input/output die size: 2.82 mm 1.50 mm 0.1 mm applications test instrumentation microwave radios and vsats military and space telecommunications infrastructure fiber optics functional block diagram 1 2 34 5 678 v gg 1 v gg 2 rfin acg4 acg3 acg1 acg2 rfout/v dd HMC930A 13738-001 figure 1. general description the HMC930A is a gallium arsenide (gaas), pseudomorphic, high electron mobility transfer (phemt), monolithic microwave integrated circuit (mmic), distributed power amplifier that operates from dc to 40 ghz. the HMC930A provides 13 db of gain, 33.5 dbm output ip3, and 22 dbm of output power at 1 db gain compression, requiring 175 ma from a 10 v supply. the HMC930A exhibits a slightly positive gain slope from 8 ghz to 32 ghz, making it ideal for electronic warfare (ew), electronic countermeasures (ecm), radar, and test equipment applications. the HMC930A amplifier inputs/outputs (i/os) are internally matched to 50 , facilitating integration into multichip modules (mcms). all data is taken with the chip connected via two 0.025 mm (1 mil) wire bonds of minimal length at 0.31 mm (12 mils).
HMC930A data sheet rev. 0 | page 2 of 16 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? electrical specifications ................................................................... 3 ? dc to 12 ghz frequency range ................................................ 3 ? 12 ghz to 32 ghz frequency range ......................................... 3 ? 32 ghz to 40 ghz frequency range ......................................... 4 ? total supply current by v dd ....................................................... 4 ? absolute maximum ratings ............................................................ 5 ? esd caution .................................................................................. 5 ? pin configuration and function descriptions ..............................6 ? interface schematics .....................................................................7 ? typical performance characteristics ..............................................8 ? theory of operation ...................................................................... 13 ? applications information .............................................................. 14 ? biasing procedures ..................................................................... 14 ? mounting and bonding techniques for millimeterwave gaas mmics ......................................................................................... 15 ? outline dimensions ....................................................................... 16 ? die packaging information ....................................................... 16 ? ordering guide ............................................................................... 16 ? revision history 12 /15revision 0 : initial version
data sheet HMC930A rev. 0 | page 3 of 16 electrical specifications dc to 12 ghz frequency range t a = 25c, v dd = 10 v, v gg 2 = 3.5 v, i dd = 175 ma. adjust v gg 1 between ?2 v to 0 v to achieve i dd = 175 ma, typical. table 1. parameter symbol test conditions/comments min typ max unit frequency range dc 12 ghz gain 11.5 13.5 db gain flatness 0.5 db gain variation over temperature 0.01 db/c return loss input 18 db output 28 db output output power for 1 db compression p1db 21 23 dbm saturated output power p sat 25 dbm output third-order intercept ip3 36 dbm noise figure 4.5 db supply current i dd v dd = 10 v, v gg 1 = ?0.8 v, typical 175 ma 12 ghz to 32 ghz frequency range t a = 25c, v dd = 10 v, v gg 2 = 3.5 v, i dd = 175 ma. adjust v gg 1 between ?2 v to 0 v to achieve i dd = 175 ma, typical. table 2. parameter symbol test conditions/comments min typ max unit frequency range 12 32 ghz gain 11 13 db gain flatness 0.3 db gain variation over temperature 0.017 db/c return loss input 16 db output 20 db output output power for 1 db compression p1db 22 dbm saturated output power p sat 24 dbm output third-order intercept ip3 33.5 dbm noise figure 5 db supply current i dd v dd = 10 v, v gg 1 = ?0.8 v, typical 175 ma
HMC930A data sheet rev. 0 | page 4 of 16 32 ghz to 40 ghz frequency range t a = 25c, v dd = 10 v, v gg 2 = 3.5 v, i dd = 175 ma. adjust v gg 1 between ?2 v to 0 v to achieve i dd = 175 ma, typical. table 3. parameter symbol test conditions/comments min typ max unit frequency range 32 40 ghz gain 10 12 db gain flatness 1.0 db gain variation over temperature 0.032 db/c return loss input 15 db output 20 db output output power for 1 db compression p1db 20 dbm saturated output power p sat 23 dbm output third-order intercept ip3 29 dbm noise figure 7.5 db supply current i dd v dd = 10 v, v gg 1 = ?0.8 v, typical 175 ma total supply current by v dd table 4. parameter symbol min typ max unit supply current i dd v dd = 9 v 175 ma v dd = 10 v 175 ma v dd = 11 v 175 ma
data sheet HMC930A rev. 0 | page 5 of 16 absolute maximum ratings table 5. parameter rating drain bias voltage (v dd ) 13 v gate bias voltage v gg 1 ?3 v to 0 v dc v gg 2 v dd = 12 v v gg 2 = 5.5 v, i dd >145 ma v dd = 8.5 v to 11 v v gg 2 = (v dd ? 6.5 v) up to 4.5 v v dd < 8.5 v v gg 2 must remain > 2 v rf input power (rfin) 22 dbm channel temperature 150c continuous power dissipation, p diss (t a = 85c, derate 69 mw/c above 85c) 2.1 w thermal resistance (channel to die bottom) 31.1c/w output power into voltage standing wave ratio (vswr) > 7:1 24 dbm storage temperature range ?65c to +150c operating temperature range ?55c to +85c esd sensitivity, human body model (hbm) class 1a, passed 250 v stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. esd caution
HMC930A data sheet rev. 0 | page 6 of 16 pin configuration and fu nction descriptions 1 2 34 5 678 v gg 1 v gg 2 rfin acg4 acg3 acg1 acg2 rfout/v dd HMC930A top view (not to scale) notes 1. die bottom must be connected to rf/dc ground. 13738-002 figure 2. pad configuration table 6. pad function descriptions pad no. mnemonic description 1 rfin rf input. this pin is dc-coupl ed and matched to 50 . a blocking ca pacitor is required on this pin. 2 v gg 2 gate control 2 for the amplifier. attach bypass capaci tors as shown in figure 37. for nominal operation, apply 3.5 v to v gg 2. 3 acg1 low frequency termination 1. attach bypass capacitors as shown in figure 37. 4 acg2 low frequency termination 2. attach bypass capacitors as shown in figure 37. 5 rfout/v dd 1 rf output for the amplifier (rfout). dc bias (v dd ). connect v dd to the bias tee network to provide the drain current (i dd ). see figure 37. 6 acg3 low frequency termination 3. attach bypass capacitors as shown in figure 37. 7 acg4 low frequency termination 4. attach bypass capacitors as shown in figure 37. 8 v gg 1 gate control 1 for the amplifier. attach bypass capaci tors as shown in figure 37. follow the procedures described in the biasing procedures section. die bottom gnd die bottom must be connected to rf/dc ground. 1 rfout/v dd is a multifunction pad.
data sheet HMC930A rev. 0 | page 7 of 16 interface schematics rfin 13738-003 figure 3. rfin interface schematic v gg 2 13738-004 figure 4. v gg 2 interface schematic acg1 rfout/v dd 13738-005 figure 5. acg1 and rfout/v dd interface schematic in acg3 13738-006 figure 6. acg3 interface schematic v gg 1 13738-007 figure 7. v gg 1 interface schematic gnd 13738-008 figure 8. gnd interface schematic
HMC930A data sheet rev. 0 | page 8 of 16 typical performance characteristics 20 ?40 ?30 ?20 ?10 0 10 05 15 10 20 25 30 35 40 45 50 response (db) frequency (ghz) s11 s21 s22 13738-009 figure 9. gain and return loss 0 ?40 ?30 ?20 ?10 04 12 8 162024283236 44 40 return loss (db) frequency (ghz) +85c +25c ?55c 13738-010 figure 10. input return loss vs. frequency for various temperatures 20 ?50 ?30 ?10 10 ?40 ?20 0 0.00001 0.0001 0.01 0.001 0.1 1 10 response (db) frequency (ghz) s11 s21 s22 13738-011 figure 11. low frequency gain and return loss 18 6 8 10 12 14 16 04 12 8 162024283236 44 40 gain (db) frequency (ghz) +85c +25c ?55c 13738-012 figure 12. gain vs. frequency for various temperatures 0 ?40 ?30 ?20 ?10 04 12 8 162024283236 44 40 return loss (db) frequency (ghz) +85c +25c ?55c 13738-013 figure 13. output return loss vs. frequency for various temperatures 10 0 4 8 2 6 036 32 28 24 20 1612 8 44 0 noise figure (db) frequency (ghz) +85c +25c ?55c 13738-014 figure 14. noise figure vs. frequency for various temperatures
data sheet HMC930A rev. 0 | page 9 of 16 30 16 20 28 18 24 26 22 03 6 32 28 24 20 1612 8 44 0 p1db (dbm) frequency (ghz) +85c +25c ?55c 13738-015 figure 15. p1db vs. frequency for various temperatures 30 18 20 28 24 26 22 036 32 28 24 20 1612 8 44 0 p sat (dbm) frequency (ghz) +85c +25c ?55c 13738-016 figure 16. p sat vs. frequency for various temperatures 30 16 18 20 28 24 26 22 036 32 28 24 20 1612 8 44 0 p1db (dbm) frequency (ghz) 125ma 175ma 13738-017 figure 17. p1db vs. frequency and supply current 30 16 20 28 18 24 26 22 03 6 32 28 24 20 1612 8 44 0 p1db (dbm) frequency (ghz) 8v 10v 11v 13738-018 figure 18. p1db vs. frequency for various supply voltages 30 18 20 28 24 26 22 036 32 28 24 20 1612 8 44 0 p sat (dbm) frequency (ghz) 8v 10v 11v 13738-019 figure 19. p sat vs. frequency for various supply voltages 30 16 18 20 28 24 26 22 036 32 28 24 20 1612 8 44 0 p sat (dbm) frequency (ghz) 125ma 175ma 13738-020 figure 20. p sat vs. frequency and supply current
HMC930A data sheet rev. 0 | page 10 of 16 42 24 26 40 32 36 38 30 34 28 036 32 28 24 20 16 12 8 440 ip3 (dbm) frequency (ghz) +85c +25c ?55c 13738-021 figure 21. output ip3 vs. frequency for various temperatures at p out = 14 dbm/tone 42 24 26 40 32 36 38 30 34 28 036 32 28 24 20 16 12 8 440 ip3 (dbm) frequency (ghz) 125ma 175ma 13738-022 figure 22. output ip3 vs. frequency and supply current at p out = 14 dbm/tone 80 0 70 30 50 60 20 40 10 014 12 10 864 216 im3 (dbc) p out /tone (dbm) 2ghz 8ghz 14ghz 20ghz 28ghz 34ghz 40ghz 13738-023 figure 23. output third-order in termodulation tone (im3) at v dd = 10 v 42 24 26 40 32 36 38 30 34 28 036 32 28 24 20 1612 8 44 0 ip3 (dbm) frequency (ghz) 8v 10v 11v 13738-024 figure 24. output ip3 vs. frequency for various supply voltages at p out = 14 dbm/tone 80 0 70 30 50 60 20 40 10 014 12 10 864 216 im3 (dbc) p out /tone (dbm) 2ghz 8ghz 14ghz 20ghz 28ghz 34ghz 40ghz 13738-025 figure 25. output im3 at v dd = 8 v 80 0 70 30 50 60 20 40 10 014 12 10 864 216 im3 (dbc) p out /tone (dbm) 2ghz 8ghz 14ghz 20ghz 28ghz 34ghz 40ghz 13738-026 figure 26. output im3 at v dd = 11 v
data sheet HMC930A rev. 0 | page 11 of 16 0 ?80 ?10 ?50 ?30 ?20 ?60 ?40 ?70 032 24 36 28 2016 12 8 44 4 40 isolation (db) frequency (ghz) +85c +25c ?55c 13738-027 figure 27. reverse isolation vs. frequency for various temperatures 35 10 30 20 25 15 125 165 155 145 135 175 gain (db), p1db (dbm), p sat (dbm) i dd (ma) gain p1db p sat 13738-028 figure 28. gain and power (p1db and p sat ) vs. supply current (i dd ) at 20 ghz 3 0 2 1 09 312 61 5 power dissipation (w) input power (dbm) 4ghz 10ghz 20ghz 30ghz 40ghz 13738-029 figure 29. power dissipation 30 0 25 5 15 20 10 250 160 235 175 205 220 190 016 12 14 10 864 218 p out (dbm), gain (db), pae (%) i dd (ma) input power (dbm) p out gain pae i dd 13738-030 figure 30. power compression at 20 ghz 35 10 30 20 25 15 810 911 gain (db), p1db (dbm), p sat (dbm) v dd (v) gain p1db p sat 13738-031 figure 31. gain and power (p1db and p sat ) vs. supply voltage (v dd ) at 20 ghz 70 0 10 50 30 20 60 40 020 16 12 8 424 second harmonic (dbc) frequency (ghz) +85c +25c ?40c 13738-032 figure 32. second-order harmonic vs. frequency for various temperatures at p out = 14 dbm, v dd = 10 v, v gg = 3.5 v, and i dd = 175 ma
HMC930A data sheet rev. 0 | page 12 of 16 70 0 10 50 30 20 60 40 020 16 12 8 424 second-order harmonic (dbc) frequency (ghz) 4dbm 6dbm 8dbm 10dbm 12dbm 14dbm 13738-033 figure 33. second-order harmonic vs. frequency for various p out values, v dd = 10 v, v gg = 3.5 v, and i dd = 175 ma 70 0 10 50 30 20 60 40 020 16 12 8 424 second-order harmonic (dbc) frequency (ghz) 8v 10v 11v 13738-034 figure 34. second-order harmonic vs. frequency for various v dd values at p out = 14 dbm and i dd = 175 ma
data sheet HMC930A rev. 0 | page 13 of 16 theory of operation the HMC930A is a gaas, phemt, mmic, cascaded, distributed power amplifier. the cascade distributed architecture uses a fundamental cell consisting of a stack of two field effect trans- istors (fets) connected from source to drain. the basic schematic for a fundamental cell is shown in figure 35. the fundamental cell is duplicated several times, with transmission lines connecting the drains of the top devices and the gates of the bottom devices, respectively. additional circuit design techniques around each cell optimize the overall response. the major benefit of this architecture is that acceptable gain is maintained across a bandwidth that is far greater than what is typically provided by a single instance of the fundamental cell. 13738-039 rfout v gg 2 v gg 1 rfin v dd figure 35. fundamental cell schematic to obtain the best performance from the HMC930A and to avoid damaging the device, follow the recommended biasing sequences described in the biasing procedures section.
HMC930A data sheet rev. 0 | page 14 of 16 applications information 4.7f = 100pf and 0.01f integrated into one case 50 ? transmission line 1mil gold wire 3mil nominal gap + + ? +? ? + ? = 0.01f = 100f 4.7f 4.7f 4.7f 13738-035 figure 36. assembly diagram + 4.7f + 4.7f + 4.7f + 4.7f 0.01f 0.01f 0.01f 0.01f 100pf 100pf 100pf 100pf acg4 acg1 1 2 3 4 5 6 7 8 acg2 v dd rfout v gg 1 rfin v gg 2 acg3 13738-036 figure 37. application circuit biasing procedures capacitive bypassing is required for both v gg 1 and v gg 2, as shown in figure 37. the capacitors to ground required for the acg1 through acg4 pads act as low frequency terminations; this helps flatten the overall frequency response by diminishing the gain at low frequencies. the recommended biasing sequence during power-up is as follows: 1. connect to gnd. 2. set v gg 1 to ?2 v to pinch off the drain current. 3. set v dd to 10 v (the drain current is pinched off). 4. set v gg 2 to 3.5 v (the drain current is pinched off). 5. adjust v gg 1 in a positive direction until a quiescent current (i dd ) of 175 ma is obtained. 6. apply the rf signal. the recommended biasing sequence during power-down is as follows: 1. tur n of f t he rf sig na l. 2. set v gg 1 to ?2 v to pinch off the drain current. 3. set v gg 2 to 0 v. 4. set v dd to 0 v. 5. set v gg 1 to 0 v. all measurements for the HMC930A are taken using the typical application circuit (see figure 37) configured as shown figure 36. the bias conditions shown in the electrical specifications section are the operating points recommended to optimize the overall performance. unless otherwise noted, the data shown is taken using the recommended bias conditions. operation of the HMC930A at different bias conditions may provide performance that differs from what is shown in the typical performance characteristics section.
data sheet HMC930A rev. 0 | page 15 of 16 mounting and bonding techniques for millimeterwave gaas mmics attach the die directly to the ground plane eutectically or with conductive epoxy (see the handling precautions section, the mounting section, and the wire bonding section). microstrip, 50 , transmission lines on 0.127 mm (5 mil) thick alumina, thin film substrates are recommended for bringing the radio frequency to and from the chip (see figure 38). when using 0.254 mm (10 mil) thick alumina thin film substrates, raise the die 0.150 mm (6 mils) to ensure that the surface of the die is coplanar with the surface of the substrate. one way to accomplish this is to attach the 0.102 mm (4 mil) thick die to a 0.150 mm (6 mil) thick, molybdenum (mo) heat spreader (moly tab), which is then attached to the ground plane (see figure 38). 0.102mm (0.004") thick gaas mmic wire bond rf ground plane 0.127mm (0.005") thick alumina thin film substrate 0.076mm (0.003") 13738-037 figure 38. die without the moly tab 0.254mm (0.010") thick alumina thin film substrate 0.150mm (0.005") thick moly tab 0.102mm (0.004") thick gaas mmic wire bond 0.076mm (0.003") rf ground plane 13738-038 figure 39. die with the moly tab place microstrip substrates as close to the die as possible to minimize bond wire length. typical die to substrate spacing is 0.076 mm to 0.152 mm (3 mil to 6 mil). handling precautions to avoid permanent damage, follow these storage, cleanliness, static sensitivity, transient, and general handling precautions: ? place all bare die in either waffle or gel-based esd protective containers and then seal the die in an esd protective bag for shipment. once the sealed esd protective bag is opened, store all die in a dry nitrogen environment. ? handle the chips in a clean environment. do not attempt to clean the chip using liquid cleaning systems. ? follow esd precautions to protect against esd strikes. ? while bias is applied, suppress instrument and bias supply transients. use shielded signal and bias cables to minimize inductive pick up. ? handle the chip along the edges with a vacuum collet or with a sharp pair of bent tweezers. the surface of the chip may have fragile air bridges and must not be touched with vacuum collet, tweezers, or fingers. mounting the chip is back metallized and can be die mounted with ausn eutectic preforms or with electrically conductive epoxy. ensure that the mounting surface is clean and flat. when attaching eutectic die, an 80/20 gold tin preform is recommended with a work surface temperature of 255c and a tool temperature of 265c. when hot 90/10 nitrogen/hydrogen gas is applied, ensure that tool tip temperature is 290c. do not expose the chip to a temperature greater than 320c for more than 20 seconds. for attachment, no more than 3 seconds of scrubbing is required. when attaching epoxy die, apply a minimum amount of epoxy to the mounting surface so that a thin epoxy fillet is observed around the perimeter of the chip once it is placed into position. cure epoxy per the schedule of the manufacturer. wire bonding rf bonds made with two 1 mil wires are recommended. ensure that these bonds are thermosonically bonded with a force of 40 grams to 60 grams. dc bonds of a 0.001 (0.025 mm) diameter, thermosonically bonded, are recommended. make ball bonds with a force of 40 grams to 50 grams and wedge bonds with a force of 18 grams to 22 grams. make all bonds with a nominal stage temperature of 150c. apply a minimum amount of ultrasonic energy to achieve reliable bonds. make all bonds as short as possible, less than 12 mils (0.31 mm).
HMC930A data sheet rev. 0 | page 16 of 16 outline dimensions 10-21-2015-a top view (circuit side) side view 1.500 2.820 1.733 0.199 0.199 0.742 1 5 2 3 4 6 7 8 0.382 0.206 0.150 0.150 0.155 0.199 0.208 0.187 0.097 0.511 0.086 0.154 0.100 0.100 0.100 figure 40. 8-pad bare die [chip] (c-8-6) dimensions shown in millimeter die packaging information standard alternate packaging gp-2 (gel pack) for alternate packaging information, contact analog devices, inc. ordering guide model temperature range packag e description package option HMC930A ?55c to +85c 8-pad bare die [chip] c-8-6 ?2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d13738-0-12/15(0)

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